1. Field of the Invention
The present invention generally relates to a method for forming integrated circuits, and more particularly to a method for forming semiconductor device by using super halo implant combined with offset spacer process.
2. Description of the Prior Art
As MOS (Metal-Oxide-Semiconductor) device scaled down to sub-0.25 .mu.m, in order to maintain enough short channel margin, tilt angle halo implant is necessary. Unfortunately, the poly spacing is also shrunk, it dose strictly limit halo tilt angle. Thus, super halo process has been proposed. Super halo process uses zero angle halo implant after poly has been defined, then lateral diffusion is performed by using thermal anneal. Following description will set forth an exemplary process of super halo process with the aid of FIG. 1A to FIG. 1D.
Referring to FIG. 1A, a substrate 100 is provided with gate oxide layer 120 and poly gate 130 formed thereon. Thus, two gate electrodes formed in an active area defined in between the isolation regions (not shown in the FIGURE). The gate oxide layer 120 is a layer of insulation to separate poly gate 130 and substrate 100. Source and drain regions will be formed in the substrate 100 at opposite ends of the gate 130. A channel region under the gate electrode 130 is located between the source and drain regions in the substrate 100. Then, super halo implant is preformed to form implant regions 112, as shown in FIG. 1B. The implant regions 112 in the substrate 100 are placed to completely separate the source and drain regions from the channel regions for improving short channel effect. The implant step needs to be performed twice, one for NMOS and the other for PMOS, and then two masks and lithography processes are applied. After the super halo implant steps, such as anneals, cause the halo dopant diffuse toward the channel region.
Subsequently, as shown in FIG. 1C, another implant occurs. This implant step is to form source/drain extension regions 114. The amount of dopant is controlled so that the dopant concentration is relatively low to source and drain regions, and the junction depth is controlled relative shallow to source/drain regions. Then, a thermal anneal is performed so that the dopant diffuses toward the area under gate electrode 130 and the gate to drain overlap will increase. Then, spacer 122 is formed on the sidewall of the gate 130, and again another implant is performed to form source/drain regions 116, as shown in FIG. 1D. The processes which follow are salicide process and backend process.
By the way, the formulation of source/drain extension region and super halo implant must be separated because of shallow junction issue. It means that the super halo process needs to increase two mask steps (one for NMOS and the other for PMOS).